Audio SC-120A Fiche technique

Audio Serial Bus InterfaceLINE 2LPPGA0/+59.5dB0.5dBStepsLeftChannelADCHPCOMHPLOUTLeftChannelDACAGCBias/ReferenceHPROUTRIGHT _LOPLEFT _LOPMIC 3R/LINE 2

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comElectrical Characteristics (continued)At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, S

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Electrical Characteristics (continued)At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SP

T0145-01WCLKBCLKSDOUTSDINt (DO-BCLK)dt (DO-WS)dt (WS)dt (DI)St (DI)hTLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comAudio Data Se

T0145-02WCLKBCLKSDOUTSDINt (WS)ht (BCLK)Ht (DO-BCLK)dt (DO-WS)dt (DI)St (BCLK)Lt (DI)ht (WS)ST0146-01WCLKBCLKSDOUTSDINt (DO-BCLK)dt (WS)dt (WS)dt (DI)

T0146-02WCLKBCLKSDOUTSDINt (WS)ht (WS)ht (BCLK)Lt (DO-BCLK)dt (DI)St (BCLK)Ht (DI)ht (WS)St (WS)STLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBE

-160-140-120-100-80-60-40-2000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20f-Frequency-kHzAmplitude-dBLoad=10k ,FS=48kHz,f =64kHz

0.10.20.40.30.60.710.9230.1 10Class-DOutputPower-mWTHD-TotalHarmonicDistortion-%1 100 10000.50.8-160-140-120-100-80-60-40-2000 1 2 3 4 5 6 7

Audio Serial Bus InterfaceLINE 2 LPPGA0/+59.5dB0.5dBStepsLeftChannelADCHPCOMHPLOUTLeftChannelDACAGCBias/ReferenceHPROUTRIGHT _LOPLEFT _LOPMIC 3R /LINE

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.com10.3 Feature Description10.3.1 Hardware ResetThe TLV320AIC3107 requires a hardwar

n-1 n-2 n-3 n-1 n-2 n-3n-1 n-2 n-3 n-1 n-2 n-3BCLKWCLKSDIN/SDOUT1 00 1 01/fsLSBMSBLeftChannel RightChannel2 2n−1n−3n−2n−1n−3n−2TLV320AIC3107www.ti.c

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable of Contents10.1 Overview ...

BCLKWCLK0 0T0152-011/fsLSB LSBLSB MSB MSBLeftChannelRightChannel1 12 2SDIN/SDOUTn–1 n–1n–1n–2n–3 n–3n–4n–2TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVI

N-1 N-2 1 0 N-1 N-2 1 0wordclockbit clockdatain/outRightChannelDataRightChannelDataLeftChannelDataLeftChannelDataN-1 N-2 1 0 N-1 N-2 1 0wordcl

K*R/P2/QPLL_CLKINCODECCODEC_CLKINPLL_OUTK=J.DJ=1,2,3,…..,62,63D=0000,0001,….,9998,9999R=1,2,3,4,….,15,16P=1,2,….,7,8Q=2,3,…..,16,17MCLK BCLKCL

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Feature Description (continued)where• P = 1, 2, 3,…, 8• R = 1, 2, …, 16• K = J.D•

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comFeature Description (continued)Table 1. Audio Clock Generation (continued)Fsref =

H(z) +N0 ) N1 z*132768 * D1 z*1TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014power down, the PGA soft-steps the volume to mu

Decay TimeTargetLevelInputSignalOutputSignalAGCGainAttackTimeTLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 2. AGC Decay T

ǒN0 ) 2 N1 z*1) N2 z*232768 * 2 D1 z*1* D2 z*2ǓǒN3 ) 2 N4 z*1) N5 z*232768 * 2 D4 z*1* D5 z*2ǓH(z) +N0 ) N1 z*132768 * D1

LB1 LB2RB1 RB2TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comThe N and D coefficients are fully programmable, and the entire fil

B0155-01LB1RB2AttenLB2L+++++––++RToLeftChannelToRightChannelTLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Figure 22. Archite

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 20146 Description (Continued)Extensive register-based power control is included, enabl

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comBecause of soft-stepping, the host does not know when the DAC has been actually m

MIC3LMIC3RPDWNLeft ADCMICDET0dBto -18dBin 0.5dBStepsLINE2LPLINE1RPLINE1LPVCMLINE1RMVCMLINE2LMLINE1LMMIC3L/LINE 1RMMIC3R/LINE2RMLINE2RP/ 2LMLINEMICD

MIC3LMIC3RPDWNRight ADC0dBto -18dBin 0.5dBStepsLINE2RP/LINE2LMLINE1LPLINE1RPVCMLINE1LMVCMLINE2RMLINE1RMMIC3L/LINE1RMMIC3R/LINE2RMVCMVCM0dB, -6dB, o

0dBto -78dB0dBto -78dB0dBto -78dB0dBto -78dB0dBto -78dB0dBto -78dB+LINE2LLINE2RPGA_LPGA_RDAC_L1DAC_R1VOLUMECONTROLS,MIXINGLINE2LLINE2RPGA_LPGA_R

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comThe DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered

Volume0dBto+9dB,muteVolume0dBto+9dB,muteVCMVolume0dBto+9dB,muteHPLOUTHPCOMHPROUTDAC_L2LINE2LLINE2RPGA_LDAC_L1DAC_R1VOLUMECONTROLS,MIXINGPGA_R

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.com10.3.7 Input Impedance and VCM ControlThe TLV320AIC3107 includes several programm

SPOMClass-DSpeakerAmplifier26Class-DGain(R73-D7-D6)Class-DEnable(R73-D3)Gain:0to+18dB6dBstepsLEFT_LOPSPVDDLSPVSSL25 24SWOUTPSWOUTM2928SWINPSWIN

MICBIASMIC3(L/R)HPLOUTHPROUTMICDETTo Detection blockssg msg m ssgStereoCellularStereo +Cellularm = mics = earspeakerg = ground/midbiasAVDDMICBIASMIC3(

ToDetectionblockHPLOUTHPCOMMICDETThisswitchcloseswhenjackisremovedTLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014An output

SDAAVSS_ADC MICBIAS LINE2LP LINE1RP IOVDDDOUTHPLOUT DRVDD AVDD_ADC DVSS DINWCLKHPROUT HPCOM DRVSS DVDD BCLKMCLKLEFT_LOP DRVDD SWINM SWINP GPIO1RESETRI

MIC3R/LINE2RMLINE2RP /LINE2LMLINE2RPLINE2RMMIC3L /LINE1RMLINE1RPLINE1RPLINE1RMMICDET/LINE1LMLINE1LPLINE1LPLINE1LMLINE2RP /LINE2LMLINE2LPLINE2

AudioSerialBusInterfacePGA0/+59.5dB0.5dBstepsADC+DACLVolumeControlDINDOUTBCLKWCLKDINLDINRDOUTLDOUTRADCPGA0/+59.5dB0.5dBsteps+DACRVolumeControlEff

SDASCLtHD-STA0.9 s³ mtSU-STO0.9 s³ mPStSU-STA0.9 s³ mSrtHD-STA0.9 s³ mSTLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comProgrammin

DA(6) DA(0) RA(7) RA(0)Start(M)7-bit Device Address(M)Write(M)SlaveAck(S)8-bit Register Address(M)SlaveAck(S)SDASCLDA(6) DA(0)7-bit Device Address(M)R

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comProgramming (continued)For example, at device reset, the active page defaults to

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 8. Page 0 / Register 2: Codec Sample Rate Select RegisterBIT READ/ RESET DES

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 10. Page 0 / Register 4: PLL Programming Register BBIT READ/ RESET DESCRIPT

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 14. Page 0 / Register 8: Audio Serial Data Interface Control Register ABIT R

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 16. Page 0 / Register 10: Audio Serial Data Interface Control Register CBIT

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 18. Page 0 / Register 12: Audio Codec Digital Filter Control RegisterBIT REA

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Pin FunctionsPINI/O DESCRIPTIONQFN WCSP(1)NAME1 A1 SCL I I2C serial clock2 B1 SDA

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 20. Page 0 / Register 14: Headset / Button Press Detection Register BBIT RE

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 23. Page 0 / Register 17: MIC3L/R to Left ADC Control RegisterBIT READ/ RESE

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 25. Page 0 / Register 19: LINE1L to Left ADC Control RegisterBIT READ/ RESE

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 27. Page 0 / Register 21: LINE1R to Left ADC Control RegisterBIT READ/ RESET

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 29. Page 0 / Register 23: LINE2R to Right ADC Control RegisterBIT READ/ RES

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 32. Page 0 / Register 26: Left AGC Control Register ABIT READ/ RESET DESCRIP

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 35. Page 0 / Register 29: Right AGC Control Register ABIT READ/ RESET DESCR

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 38. Page 0 / Register 32: Left AGC Gain RegisterBIT READ/ RESET DESCRIPTIONW

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 41. Page 0 / Register 35: Right AGC Noise Gate Debounce RegisterBIT READ/ R

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 43. Page 0 / Register 37: DAC Power and Output Driver Control RegisterBIT RE

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.com8 Specifications8.1 Absolute Maximum Ratingsover operating free-air temperature r

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 47. Page 0 / Register 41: DAC Output Switching Control RegisterBIT READ/ RE

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 50. Page 0 / Register 44: Right DAC Digital Volume Control RegisterBIT READ/

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 51. Output Stage Volume Control Settings and Gains (continued)Gain Setting

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 57. Page 0 / Register 50: DAC_R1 to HPLOUT Volume Control RegisterBIT READ/

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 62. Page 0 / Register 55: LINE2R to HPCOM Volume Control RegisterBIT READ/

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 67. Page 0 / Register 60: PGA_L to HPROUT Volume Control RegisterBIT READ/ R

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 72. Page 0 / Register 65: HPROUT Output Level Control RegisterBIT READ/ RES

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 79. Page 0 / Register 72: ReservedBIT READ/ RESET DESCRIPTIONWRITE VALUED7–D

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 83. Page 0 / Register 76: ADC DC Dither Control RegisterBIT READ/ RESET DES

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 88. Page 0 / Register 81: PGA_L to LEFT_LOP Volume Control RegisterBIT READ/

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 20148.4 Thermal InformationTLV320AIC3107THERMAL METRIC(1)RSB YZF UNIT40 PINS 42 PINSRθ

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 93. Page 0 / Register 86: LEFT_LOP Output Level Control RegisterBIT READ/ R

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 98. Page 0 / Register 91: PGA_R to RIGHT_LOP Volume Control RegisterBIT READ

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 101. Page 0 / Register 94: Module Power Status RegisterBIT READ/ RESET DESC

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 103. Page 0 / Register 96: Sticky Interrupt Flags RegisterBIT READ/ RESET DE

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 105. Page 0 / Register 98: GPIO1 Control RegisterBIT READ/ RESET DESCRIPTIO

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 106. Page 0 / Register 99: ReservedBIT READ/ RESET DESCRIPTIONWRITE VALUED7–

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 111. Page 0 / Register 104: Left AGC Programmable Decay Time Register(1)BIT

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 113. Page 0 / Register 106: Right AGC New Programmable Decay Time Register(1

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 115. Page 0 / Register 108: Passive Analog Signal Bypass Selection During P

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 119. Page 1 / Register 1: Left Channel Audio Effects Filter N0 Coefficient M

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.com8.6 Electrical CharacteristicsAt 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SPVDD = 5

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 127. Page 1 / Register 9: Left Channel Audio Effects Filter N4 Coefficient

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 134. Page 1 / Register 17: Left Channel Audio Effects Filter D4 Coefficient

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 142. Page 1 / Register 25: Left Channel De-emphasis Filter D1 Coefficient M

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 150. Page 1 / Register 33: Right Channel Audio Effects Filter N3 Coefficient

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 158. Page 1 / Register 41: Right Channel Audio Effects Filter D2 Coefficien

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 166. Page 1 / Register 49: Right Channel De-emphasis Filter N1 Coefficient M

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comTable 174. Page 1 / Register 66: Left Channel ADC High Pass Filter N0 Coefficient

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Table 182. Page 1 / Register 74: Right Channel ADC High Pass Filter N1 Coefficient

AIC3107LINE2LPLINE1LPLINE1RPMIC 3L/LINE1RM0.47mFMICBIASA2k W0.47mFAVDD_DACAVSS_DACDRVDDDVSSIOVDDDRVDDDRVSSAVDD_ADCAVSS_ADCAD1.525-1.95VIOVDD(1.1-3.3V)

1.522.533.542.7 2.9 3.1 3.3 3.5V -SupplyVoltage-VDDMICBIAS -VVOLTAGENoLoadPGM=VDDPGM=2VPGM=2.5V-90-80-70-60-50-40-30-20-1000 20 40 60 80

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014Electrical Characteristics (continued)At 25°C, AVDD_DAC = 3.3 V, DRVDD = 3.3 V, SP

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.com12 Power Supply RecommendationsThe TLV320AIC3107 has been designed to be extremel

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 201413.2 Layout ExampleFigure 41. AIC3107 WQFN Layout ExampleCopyright © 2008–2014, Te

TLV320AIC3107SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014www.ti.comLayout Example (continued)Figure 42. AIC3107 DSBGA Layout Example92 Submit Docume

TLV320AIC3107www.ti.comSLOS545D –NOVEMBER 2008–REVISED DECEMBER 201414 Device and Documentation Support14.1 TrademarksI2C is a trademark of Philips El

PACKAGE OPTION ADDENDUMwww.ti.com27-Oct-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

PACKAGE OPTION ADDENDUMwww.ti.com27-Oct-2014Addendum-Page 2Important Information and Disclaimer:The information provided on this page represents TI&ap

TAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W

*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)TLV320AIC3107IRSBR WQFN RSB 40 3000 367.0 36